Abstract: As CMOS processes have been scaled down, high density plasma assisted chemical vapor deposition (HDPCVD) has been widely used for dielectric layer filling processes, including shallow trench isolation (STI), pre-metallic dielectric layer (PMD), and intermetallic dielectric layer (IMD) due to its excellent gap filling capability, consistent deposition quality and reliable electrical performance. However, there are inherent constraints in HDPCVD technology, including cavity defects in dielectric filling and charging damage, which limit the further development of HDPCVD technology. This paper focuses on the mechanism of formation of both defects and their improvement by changing the process formulation and process flow, and finally concludes and presents an outlook.