面向5nm CMOS技术代堆叠纳米线释放工艺研究

曹志军; 张青竹; 吴次南; 闫江; 王桂磊; 李俊杰; 张兆浩; 殷华湘; 余金中; 李志华

doi:10.13922/j.cnki.cjovst.2018.02.08

面向5nm CMOS技术代堆叠纳米线释放工艺研究

Release of Stacked Nanowires for 5 nm CMOS Node: An Experimental Study

摘要

摘要: 针对5 nm CMOS技术代亟待解决的纳米线释放难题, 通过实验探究了HF (6%) ∶H₂O₂ (30%) ∶CH₃COOH (99.8%) =1∶2∶3的混合溶液放置时间对纳米尺度外延堆叠GeSi/Si/GeSi/Si结构释放影响。混合溶液放置时间在48 h内, GeSi层的腐蚀速率会随着溶液的放置时间的增加而变大, 48 h后腐蚀速率趋于稳定。另外, 在厚度相同的情况下, Ge Si层的腐蚀速率会随着Ge含量的增加而变大。本文实现了腐蚀纳米尺度GeSi的同时没有对Si造成损伤, 对于厚度为31.3 nm的GeSi层, 腐蚀的深宽比达到了17∶1, 而且没有出现倒塌现象。该湿法腐蚀工艺对于5 nm及以下技术代堆叠纳米线制造、SON结构、新型MEMS和传感器件制造等具有一定的借鉴和指导意义。

Abstract: Herein, we experimentally addressed the release of stacked nanowire (SNW) for 5 nm CMOS node via wet etching. The influence of the holding time of the Ge Si/Si/Ge Si/Sistacked nano-array in HF-H₂O₂-CH₃COOH solution on the selective etching-rate of the Ge Si sacrifice layer was investigated with scanning electron microscopy, high resolution X-ray diffraction and transmission electron microscopy. The results show that the etching-rate of Ge Si layer depends on the holding time and Ge-content. For example, as the holding time increased, the etching-rate linearly increased, levelling off after 48 h; and with a fixed thickness of Ge Si layer, the etching-rate increased with an increase of the Ge-content.The well-defined nano-structured Ge Si, with a depth-to-width ratio of 17∶1 and without a bending problem, was successfully fabricated by wet-etching of the 31. 3 nm Ge Si layer under the optimized conditions.

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