Optimization of Shallow Trench Isolation in Fabrication of Stacked Nanowire MOS Devices

Herein, we experimentally addressed the uniformity control and regulation of low-temperature Si_O2 etch-back corrosion-rate in high aspect ratio process (HARP) in forming shallow trench isolation (STI) for the stacked nanowire MOS devices with feature size of and/or below 5 nm. The influence of the annealing temperature/time and SiO₂ thickness, on the SiO₂ corrosion-rate, etched back with HF solution in low temperature HARP, was investigated. The results show that the annealing time and SiO₂ thickness had a major impact. For example, as the annealing time (at a fixed annealing temperature) increased, the SiO₂ corrosion-rate decreased; depending on the thickness, the SiO₂ corrosion-rate, in the same layer, was maximized at the top and minimized at the bottom. We suggest that the results reported here be of some technological interest in fabrication of STI structure of stacked nanowire devices with a feature-size of and/or below 5 nm.