Release of Stacked Nanowires for 5 nm CMOS Node: An Experimental Study

Herein, we experimentally addressed the release of stacked nanowire (SNW) for 5 nm CMOS node via wet etching. The influence of the holding time of the Ge Si/Si/Ge Si/Sistacked nano-array in HF-H₂O₂-CH₃COOH solution on the selective etching-rate of the Ge Si sacrifice layer was investigated with scanning electron microscopy, high resolution X-ray diffraction and transmission electron microscopy. The results show that the etching-rate of Ge Si layer depends on the holding time and Ge-content. For example, as the holding time increased, the etching-rate linearly increased, levelling off after 48 h; and with a fixed thickness of Ge Si layer, the etching-rate increased with an increase of the Ge-content.The well-defined nano-structured Ge Si, with a depth-to-width ratio of 17∶1 and without a bending problem, was successfully fabricated by wet-etching of the 31. 3 nm Ge Si layer under the optimized conditions.